Texas Instruments AM62x/AM62x-Q1 Arm®-Based Low-Cost MPUs

Texas Instruments AM62x/AM62x-Q1 Arm^®-Based Low-Cost MPUs are built for Linux^® application development with scalable Arm^® Cortex^®-A53 performance and embedded features. These devices include dual-display support, 3D graphics acceleration, and an extensive set of peripherals. The AM62x/AM62x-Q1 MPUs are well-suited for a broad range of automotive and industrial applications while offering intelligent features and optimized power architecture. The AM62x-Q1 devices are AEC-Q100 qualified for automotive applications.

The 3-port Gigabit Ethernet switch has one internal and two external ports with Time-Sensitive Networking (TSN) support. An additional PRU module on the device enables real-time I/O capability. In addition, the extensive set of peripherals included in AM62x/AM62x-Q1 MPUs enable system-level connectivity, such as MMC/SD, USB, OSPI, Camera interface, CAN-FD, and GPMC for parallel host interface to an external ASIC/FPGA. The AM62x devices also support secure boot for IP protection with the built-in Hardware Security Module (HSM). These devices employ advanced power management support for portable and power-sensitive applications.

Features

Processor Cores:
- Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
- Single-core Arm Cortex-M4F MCU at up to 400MHz
- Dedicated device/power manager
Multimedia:
- Display subsystem
- 3D Graphics Processing Unit
- One Camera Serial interface (CSI-Rx) - 4 Lane with DPHY
Memory Subsystem:
- Up to 816KB of On-chip RAM
- DDR Subsystem (DDRSS)
Functional Safety:
- Functional Safety-Compliant targeted [Industrial]
  - Devices developed for functional safety applications
  - Documentation will be available to aid IEC 61508 functional safety system design
  - Systematic capability up to SIL 3 targeted
  - Hardware Integrity up to SIL 2 targeted
  - Safety-related certification
    - IEC 61508 by TUV SUD planned
- AEC-Q100 qualified
Security:
- Secure boot supported
- Cryptographic acceleration supported
- Debugging security
- Trusted Execution Environment (TEE) supported
- Secure storage support
- On-the-Fly encryption support for OSPI interface in XIP mode
PRU Subsystem:
- Dual-core Programmable Real-Time Unit Subsystem (PRUSS) running up to 333MHz
- Intended for driving GPIO for cycle-accurate protocols such as additional:
  - General Purpose Input/Output (GPIO)
  - UARTs
  - I²C
  - External ADC
- 16KByte program memory per PRU with SECDED ECC
- 8KB data memory per PRU with SECDED ECC
- 32KB general-purpose memory with SECDED ECC
- CRC32/16 HW accelerator
- Scratch PAD memory with three banks of 30 x 32-bit registers
- One industrial 64-bit timer with nine capture and 16 compare events, along with slow and fast compensation
- One interrupt controller (INTC), minimum of 64 input events supported

High-Speed Interfaces:
- Integrated Ethernet switch supporting (total of two external ports)
- Two USB2.0 ports
General Connectivity:
- 9x Universal Asynchronous Receiver-Transmitters (UART)
- 5x Serial Peripheral Interface (SPI) controllers
- 6x Inter-Integrated Circuit (I²C) ports
- 3x Multichannel Audio Serial Ports (McASP)
- 3x enhanced PWM modules (ePWM)
- 3x enhanced Quadrature Encoder Pulse modules (eQEP)
- 3x enhanced Capture modules (eCAP)
- General-purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
- 3x Controller Area Network (CAN) modules with CAN-FD support
Media and Data Storage:
- 3x Secure Digital (SD) (4b+4b+8b) interface
- 1× General-Purpose Memory Controller (GPMC) up to 133MHz
- OSPI/QSPI with DDR / SDR support
Power Management:
- Low power modes supported by device/power manager
Optimal Power Management Solution:
- Recommended TPS65219 Power Management ICs (PMIC)
Boot Options:
- UART
- I²C EEPROM
- OSPI/QSPI Flash
- GPMC NOR/NAND Flash
- Serial NAND Flash
- SD Card
- eMMC
- USB (host) boot from Mass Storage device
- USB (device) boot from an external host (DFU mode)
- Ethernet
Technology / Package:
- 16nm technology
- 13mm x 13mm, 0.5mm pitch, 425-pin FCCSP BGA (ALW)