SN74AC2G100PWR

Texas Instruments
595-SN74AC2G100PWR
SN74AC2G100PWR

Mfr.:

Description:
Flip-Flops Two-channel 1.5V to 6V configurable gat

Lifecycle:
New Product:
New from this manufacturer.
ECAD Model:
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In Stock: 3,000

Stock:
3,000 Can Dispatch Immediately
Factory Lead Time:
18 Weeks Estimated factory production time for quantities greater than shown.
Long lead time reported on this product.
Minimum: 1   Multiples: 1
Unit Price:
₹-.--
Ext. Price:
₹-.--
Est. Tariff:
Packaging:
Full Reel (Order in multiples of 3000)

Pricing (INR)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™
₹52.18 ₹52.18
₹36.43 ₹364.30
₹32.71 ₹817.75
₹28.42 ₹2,842.00
₹26.46 ₹6,615.00
₹25.25 ₹12,625.00
₹24.60 ₹24,600.00
Full Reel (Order in multiples of 3000)
₹22.92 ₹68,760.00
₹22.27 ₹1,33,620.00
† A MouseReel™ fee of ₹475.00 will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable.

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Flip-Flops
RoHS:  
D-Type
2 Circuit
Push-Pull
TSSOP-16
Schmitt-Trigger
Non-Inverting
9.7 ns
- 24 mA
24 mA
1.5 V
6 V
SMD/SMT
- 40 C
+ 125 C
Reel
Cut Tape
MouseReel
Brand: Texas Instruments
Maximum Clock Frequency: 175 MHz
Number of Input Lines: 6 Line
Number of Output Lines: 1 Line
Product Type: Flip Flops
Series: SN74AC2G100
Factory Pack Quantity: 3000
Subcategory: Logic ICs
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Compliance Codes
USHTS:
8542390090
TARIC:
8542319000
MXHTS:
8542399999
ECCN:
EAR99
Origin Classifications
Country of Origin:
Malaysia
Assembly Country of Origin:
Malaysia
Country of Diffusion:
United States
The country is subject to change at the time of shipment.

SN74AC2G100/SN74AC2G100-Q1 Dual Flip-Flops

Texas Instruments SN74AC2G100/SN74AC2G100-Q1 Dual Flip-Flops offer two independent D-type flip-flops with a rising-edge triggered clock, active low clear, and configurable logic data inputs. The data inputs can be arranged for many 1- and 2-input logic functions, including buffer, inverter, AND, OR, NAND, NOR, XOR, and XNOR. All inputs have a Schmitt-trigger architecture to support slow or noisy input signals.