SN65LVDS301 27-Bit Parallel-to-Serial Transmitter

Texas Instruments SN65LVDS301 Programmable 27-Bit Parallel-to-Serial Transmitter device converts 27 parallel data inputs to 1, 2, or 3 Sub Low-Voltage Differential Signaling (SubLVDS) serial outputs. It loads a shift register with 24-pixel bits and three control bits from the parallel CMOS input interface. In addition to the 27 data bits, the device adds a parity bit and two reserved bits into a 30-bit data word. The pixel clock (PCLK) latches each word into the device. The parity bit (odd parity) allows a receiver to detect single-bit errors. The serial shift register is uploaded at 30, 15, or 10 times the pixel-clock data rate, depending on the number of serial links used. A copy of the pixel clock is outputted as a separate differential output.