Accesses begin with the registration of the Bank Activate command, and then it is followed by a Read or Write command. Read and write accesses to the DDR2 SDRAM are 4 or 8-bit burst oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Operating the eight memory banks in an interleaved fashion allows random access operation to occur at a higher rate. An auto precharge function may be enabled to provide a self-timed row precharge. The self-timed row precharge is initiated at the end of the burst sequence. A sequential and gapless data rate is possible depending on burst length, CAS latency, and speed grade of the device.