Alliance Memory MT41x DDR3 SDRAMs use double data rate architecture with an interface to transfer two data words per clock cycle at I/O pins. The MT41x DDR3's double data rate architecture is an 8n-prefetch architecture that helps to achieve high-speed operations. These SDRAMs operate from CK and CK# differential clock inputs. The MT41x DDR3 employs a burst-orientated approach to read and write with access starting at the selected location and continuing in a programmed sequence. These SDRAMs use READ and WRITE BL8 and BC4. The MT41x DDR3 SRAMs can operate concurrently due to their pipelined and multibank architecture. This helps in providing high bandwidth by hiding row precharge and activation time. These SDRAMs feature self-refresh mode, power-saving mode, and power-down mode.
Differential bidirectional data strobe
8n-bit prefetch architecture
CK and CK# differential clock inputs
Eight internal banks
Nominal and dynamic On-Die Termination (ODT) for data, strobe, and mask signals
Programmable CAS (READ) Latency (CL)
Programmable posted CAS Additive Latency (AL)
Programmable CAS (WRITE) Latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4
Selectable BC4 or BL8 On-The-Fly (OTF)
Self Refresh Temperature (SRT)
Automatic Self Refresh (ASR)
Output driver calibration
Alliance Memory DDR3L SDRAM
DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation.