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GSI Technology SigmaQuad-II+ SRAMs

GSI Technology SigmaQuad-II+ SRAMs have built-in compliance with the SigmaQuad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. The SigmaQuad-II+ are 301,989,888-bit (288Mb) SRAMs. The SigmaQuad-II+ SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

Features

  • 2.0 or 2.5 clock latency
  • Simultaneous Read and Write SigmaQuad™ Interface 
  • JEDEC-standard pinout and package
  • Dual Double Data Rate interface
  • Byte Write controls sampled at data-in-time
  • Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs
  • Burst of 2 or 4 Read and Write
  • 1.8V ±100mV core power supply
  • 1.5V or 1.8V HSTL Interface
  • Pipelined read operation
  • Fully coherent read and write pipelines
  • ZQ pin for programmable output drive strength
  • Data Valid Pin (QVLD) Support
  • IEEE 1149.1 JTAG-compliant Boundary Scan
  • RoHS-compliant 165-bump BGA package

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Published: 2019-06-26 | Updated: 2023-09-15