Infineon Technologies CYT4BF TRAVEO™ T2G 32-bit Automotive MCUs
Infineon Technologies CYT4BF TRAVEO™ T2G 32-bit Automotive MCUs target automotive systems such as high-end body-control units, zone control, and sound systems. CYT4BF features two Arm® Cortex®-M7 CPUs for primary processing and an Arm® Cortex®-M0+ CPU for peripheral and security processing. These devices contain embedded peripherals supporting a Controller Area Network with Flexible Data (CAN FD) rate, a Local Interconnect Network (LIN), Gigabit Ethernet, and FlexRay. TRAVEO™ T2G devices are manufactured on an advanced 40nm process. CYT4BF incorporates a low-power flash memory and multiple high-performance analog and digital peripherals. The Infineon Technologies CYT4BF TRAVEO™ T2G 32-bit Automotive MCUs enable the creation of secure computing platforms.
Features
- CPU subsystem
- 2x 350MHz (maximum) 32-bit Arm Cortex-M7 CPU, each with
- Single-cycle multiply
- Single/double-precision floating point unit (FPU)
- Memory protection unit (MPU)
- 16KB instruction and 16KB data tightly coupled memories (TCM)
- 100MHz (maximum) 32-bit Arm Cortex M0+ CPU with
- Single-cycle multiply
- Memory protection unit
- Inter-processor communication in hardware
- 3x DMA controllers
- Peripheral DMA controller #0 (P-DMA0) with 143x channels
- Peripheral DMA controller #1 (P-DMA1) with 65x channels
- Memory DMA controller #0 (M-DMA0) with 8x channels
- 2x 350MHz (maximum) 32-bit Arm Cortex-M7 CPU, each with
- Integrated memories
- 8384KB of code-flash with additional 256KB of work-flash
- Read-While-Write (RWW) allows updating the code-flash/work-flash while executing code from it
- Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])
- Flash programming through the SWD/JTAG interface
- 1024KB of SRAM with selectable retention granularity
- 8384KB of code-flash with additional 256KB of work-flash
- Cryptography engine
- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)
- Secure boot and authentication
- AES: 128-bit blocks, 128-/192-/256-bit keys
- 3DES: 64-bit blocks, 64-bit key
- Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve (ECC)
- SHA-1/2/3: SHA-512, SHA-256, and SHA-160 with variable length input data
- CRC: supports CCITT CRC16 and IEEE-802.3 CRC32
- True random number generator (TRNG) and pseudo-random number generator (PRNG)
- Galois/Counter Mode (GCM)
- Functional safety for ASIL-B
- Low-power 2.7V to 5.5V operation
- Wakeup support
- Multiple clock sources
- Communication interfaces
- External memory interface
- SDHC interface
- Audio interface
- Timers
- Up to 102x 16-bit and 16x 32-bit timer/counter pulse-width modulator (TCPWM) blocks
- Up to 16x Event Generation (EVTGEN) timers supporting cyclic wake-up from DeepSleep, events trigger a specific device operation (such as execution of interrupt handler, a SAR ADC conversion, and so on)
- Real-time clock (RTC)
- I/O
- Up to 240x programmable I/Os
- 3x I/O types
- Regulators
- Generates 1.1V nominal core supply from a 2.7V to 5.5V input supply
- 3x types of regulators
- Programmable analog
- 3x SAR A/D converters with up to 99x external channels (96x I/Os + 3x I/Os for motor control)
- Each ADC supports 12-bit resolution and sampling rates of up to 1Msps
- Each ADC also supports up to 6x internal analog inputs such as
- Each ADC supports addressing external multiplexers
- Each ADC has a sequencer supporting autonomous scanning of configured channels
- Synchronized sampling of all ADCs for motor-sense applications
- Smart I/O
- Up to 5x Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os
- Up to 36x I/Os (GPIO_STD) supported
- Debug interface
- JTAG controller and interface compliant with IEEE-1149.1-2001
- Arm® SWD (serial wire debug) port
- Supports Arm® Embedded Trace Macrocell (ETM) trace
- Compatible with industry-standard tools, GHS/MULTI or IAR EWARM for code development and debugging
- Package options
- 176-TEQFP, 24mm × 24mm × 1.7mm (maximum), 0.5mm lead pitch
- 272-BGA, 16mm × 16mm × 1.7mm (maximum), 0.8mm ball pitch
- 320-BGA, 17mm × 17mm × 1.7mm (maximum), 0.8mm ball pitch
- Qualified for automotive applications according to AEC-Q100
Applications
- Body control modules and body domain control
- Zone control
- Lighting systems
- Cockpit domain control sub-systems
- Sound systems
Block Diagram
Application Notes
- AN218629: Comparison of TRAVEO T1G and TRAVEO T2G
- AN219944: Using the watchdog timer in TRAVEO T2G family MCUs
- AN220152: How to retain RAM data in reset procedure and low-power mode transition in TRAVEO family
- AN220191: How to use Direct Memory Access (DMA) controller in TRAVEO T2G family
- AN220193: GPIO usage setup in TRAVEO T2G family
- AN220224: How to use Timer, Counter, and PWM (TCPWM) in TRAVEO T2G family
- AN220242: Flash accessing procedure for TRAVEO T2G family
- AN220278: CAN FD usage in TRAVEO T2G family
- AN224413: How to Use I2S in TRAVEO T2G family
- AN225346: Using the LIN in TRAVEO T2G family
- AN225401: How to use Serial Communications Block (SCB) in TRAVEO T2G family
- AN226043: How to use sound subsystem in TRAVEO T2G family
- AN229058: Secured Firmware Over-the-Air (FOTA) update in TRAVEO T2G MCU
Additional Resources
Development Tools
Infineon Technologies CYTVII-B-H-176-SO TRAVEO™ T2G Evaluation Board
A 176-pin socketed evaluation board based on the TRAVEO™ T2G CYT4BF family of devices.
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