STMicroelectronics SPC58 32-bit Power Architecture® Microcontrollers

STMicroelectronics SPC58 MCUs are 32-bit Power Architecture® MCUs targeting body, networking, and security applications. These applications secure onboard communication systems in connected vehicles. The STMicroelectronics SPC58 is built on the successful SPC56 MCUs in ST's embedded 90nm Flash technology. This generation offers the widest range of compatible and scalable devices.

Features

  • AEC-Q100 qualified
  • High-performance e200z4 triple-core
    • 32-bit Power Architecture technology CPU
    • Core frequency as high as 180MHz
    • Variable Length Encoding (VLE)
    • Floating Point, End-to-End Error Correction
  • 6582KB (6144KB code flash+ 256KB data flash) on-chip flash memory
    • Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
    • Supports read while reading between the two code Flash partitions.
  • 608KB on-chip general-purpose SRAM (in addition to 160KB core local data RAM): 64KB in CPU_0, 64KB in CPU_1, and 32KB in CPU_2
  • 182KB HSM dedicated flash memory (144KB code + 32KB data)
  • Multi-channel direct memory access controller (eDMA)
    • one eDMA with 64 channels
    • one eDMA with 32 channels
  • 1 interrupt controller (INTC)
  • Comprehensive new generation ASIL-D safety concept
    • ASIL-D of ISO 26262
    • One CPU channel in lockstep
    • Logic BIST
    • FCCU for collection and reaction to failure notifications
    • Memory BIST
    • Cyclic redundancy check (CRC) unit
    • Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
  • Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC
  • Body cross triggering unit (BCTU)
    • Triggers ADC conversions from any eMIOS channel
    • Triggers ADC conversions from up to 2 dedicated PIT_RTIs
  • Enhanced modular IO subsystem (eMIOS): up to 64 timed IO channels with a 16-bit counter resolution
  • Enhanced analog-to-digital converter system with
    • 4 independent fast 12-bit SAR analog converters
    • One supervisor 12-bit SAR analog converter
    • One standby 10-bit SAR analog converter
  • Communication interfaces
    • 18 LINFlexD modules
    • 10 deserial serial peripheral interface (DSPI) modules
    • 8 MCAN interfaces with an advanced shared memory scheme and ISO CAN-FD support
    • Dual-channel FlexRay controller
    • Two independent Ethernet controllers
      10/100Mbps compliant IEEE 802.3-2008
  • Low power capabilities
    • Versatile low-power modes
    • Ultralow power standby with RTC
    • Smart Wake-up Unit for contact monitoring
Published: 2019-02-04 | Updated: 2024-03-20