Texas Instruments SN65LVDS93B/SN65LVDS93B-Q1 LVDS SerDes Transmitter
Texas Instruments SN65LVDS93B / SN65LVDS93B-Q1 LVDS SerDes (Serializer/Deserializer) Transmitter contains four 7-bit parallel load serial-out shift registers. The device also has a 7 × clock synthesizer and five low-voltage differential signaling (LVDS) drivers. This is all included in a single integrated circuit. These functions allow synchronous transmission of 28 bits of single-ended LVTTL data over five balanced-pair conductors for receipt by a compatible receiver, such as the DS90CR286A and SN65LVDS94. The SN65LVDS93B-Q1 devices are AEC-Q100 qualified for automotive applications.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected through the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The Texas Instruments SN65LVDS93B/SN65LVDS93B-Q1 devices require no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver, with the data transmission transparent to the users. The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input and the possible use of the shutdown/clear (SHTDN) signal. SHTDN is an active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers at a low level.
Features
- Industrial temperature range of –40°C to 85°C
- LVDS display Serdes interfaces directly to LCD display panels with integrated LVDS
- 8.1mm × 14mm TSSOP package option
- 1.8V up to 3.3V tolerant data inputs to connect directly to low-power, low-voltage applications, and graphic processors
- Transfer rate up to 85Mpps (megapixels per second); pixel clock frequency range of 10MHz to 85MHz; max 2.38Gbps data rate supported
- Suited for display resolutions ranging from HVGA up to HD with low EMI
- Operates from a single 3.3V supply and 170mW (typical) at 75MHz
- 28 data channels plus clock in low-voltage TTL to 4 data channels plus clock out low-voltage differential
- Consumes less than 1mW when disabled
- Selectable rising or falling clock edge-triggered inputs
- ESD of 5kV HBM
- Supports Spread Spectrum Clocking (SSC)
- Supports RGB 888 to LVDS I conversion
Applications
- HMI panel (Human Machine Interface)
- Industrial PC display
- Medical imaging display
- LCD display panel driver
Datasheets
Functional Block Diagram
