Texas Instruments TMS320C6412 Fixed-Point Digital Signal Processor

This device delivers up to 5760 million instructions per second (MIPS) at a clock rate of 720MHz. The TMS320C6412 device offers cost-effective solutions for high-performance DSP programming challenges. The TMS320C6412 DSP possesses the numerical capability of array processors and the operational flexibility of high-speed controllers. The C64x DSP core processor has 64 general-purpose registers with 32-bit word length and eight highly independent functional units (six arithmetic logic units (ALUs) and two multipliers for a 32-bit result) with VelociTI.2 extensions.

The TMS320C6412 has a powerful and diverse set of peripherals and uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 128Kbit direct-mapped cache, and the Level 1 data cache (L1D) is a 128Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 2Mbit memory space shared between data and program spaces. L2 memory can be configured as mapped memory, a cache, or a combination of the two.

The peripheral set includes: a 10/100Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; two multichannel buffered serial ports (McBSPs); an inter-integrated circuit (I²C) Bus module; three 32-bit general-purpose timers; a peripheral component interconnect (PCI); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and peripherals and asynchronous memories.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the TMS320C6412 DSP core processor and the network. The TMS320C6412 EMAC supports both 10Base-T and 100Base-TX, or 10Mbps and 100Mbps in either half- or full-duplex, with quality of service (QOS) support and hardware flow control. The TMS320C6412 EMAC uses a custom interface to the DSP core, enabling efficient data transmission and reception.

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to enumerate all PHY devices in the system. Once the DSP has selected a PHY candidate, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the device's link status without continuously performing costly MDIO accesses.

The I2C0 port on the Texas Instruments TMS320C6412 enables the DSP to control peripheral devices and communicate with a host processor easily. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.