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AS4C1M16S-7TCN

Name: Alliance Memory AS4C1M16S-7TCN
Brand: Alliance Memory
SKU: 913-AS4C1M16S-7TCN
Price: 471.49 INR
Availability: OutOfStock

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See Product Specifications

Mouser No:

913-AS4C1M16S-7TCN

Mfr. No:

AS4C1M16S-7TCN

Mfr.:

Alliance Memory

Description:

DRAM SDRAM, 16Mb, 1M x 16, 3.3V, 50pin TSOP II, 143 MHz, Commercial Temp - Tray

Datasheet:

AS4C1M16S-7TCN Datasheet (PDF)

ECAD Model:

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More Information

Learn more about Alliance Memory AS4C1M16S-7TCN

Availability

Stock:: 0

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On Order:: 234

Expected 29-05-2026
Factory Lead Time:: 12

Weeks Estimated factory production time for quantities greater than shown.

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Ext. Price:

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Est. Tariff:

Pricing (INR)

Qty.	Unit Price	Ext. Price
	₹471.49	₹471.49
	₹438.88	₹4,388.80
	₹425.83	₹10,645.75
	₹416.51	₹20,825.50
	₹406.26	₹47,532.42
	₹393.22	₹92,013.48
	₹383.90	₹2,24,581.50
	₹374.58	₹3,94,432.74

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Alliance Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM
Memory Size:	16 Mbit
Data Bus Width:	16 bit
Maximum Clock Frequency:	143 MHz
Package/Case:	TSOP-II-50
Organisation:	1 M x 16
Access Time:	5.4 ns
Supply Voltage - Min:	3 V
Supply Voltage - Max:	3.6 V
Minimum Operating Temperature:	0 C
Maximum Operating Temperature:	+ 70 C
Series:	AS4C1M16S-7
Packaging:	Tray
Brand:	Alliance Memory
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	117
Subcategory:	Memory & Data Storage
Supply Current - Max:	70 mA

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Filter Document:

Datasheet

AS4C1M16S-7TCN Datasheet (PDF)

REACH Declaration (PDF)

Compliance Codes

CNHTS:: 8542329000
USHTS:: 8542320002
JPHTS:: 854232021
KRHTS:: 8542321010
MXHTS:: 8542320201
ECCN:: EAR99

Origin Classifications

Country of Origin:: Taiwan
Assembly Country of Origin:: Taiwan
Country of Diffusion:: Taiwan

The country is subject to change at the time of shipment.

AS4C SDRAM

Alliance Memory AS4C SDRAM is high-speed CMOS synchronous DRAM containing 64Mbits, 128Mbits, or 256Mbits. They are internally configured as 4 banks of 1M, 2M, or 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented, accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command, which is then followed by a Read or Write command.