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Bench Talk for Design Engineers

Bench Talk


Bench Talk for Design Engineers | The Official Blog of Mouser Electronics

Using PMIC to Manage Power for SoCs Adam Kimmel

(Source: graphicINmotion/

New technology and applications, coupled with tighter packaging and increased connectivity requirements, push the limits of current processors and their power systems. These processors must support computing with increasing amounts of audio, video, high-definition (HD) graphics, streaming, gaming, and everything in between. As the volume and quality of content go up, so too does the desire to offer improved performance in less space. This user-driven approach pulls integration to the forefront, making it a limiting factor in technology development.

The challenge to achieve high performance while reducing cost led engineers to develop the System on a Chip (SoC) integrated circuits (IC.) These solutions integrate many system functionalities into an IC, reducing power consumption, cost, and effort as well as technical knowledge required to implement functions that otherwise call for deep domain expertise such as video and graphics processing. Achieving high performance at a palatable cost dictates that manufacturers develop SoCs in a deep sub-micron (complementary metal–oxide–semiconductor (CMOS), ≤ 16/14nm) process.

Such SoCs require power supplies to provide high current, which can be a challenge to realize in advanced sub-micron CMOS processes. Power supply circuits require large transistors to handle high currents and to withstand high voltage (relative to the digital core voltage). These attributes are diametrically opposite to those associated with transistors used in digital circuits. Therefore, it is technically challenging (or impossible) to implement power supplies on the same die as the digital circuits, and it’s likely not economical to do so. By and large, these incompatibilities have always existed in IC design, but they are amplified as modern processors are implemented in ever shrinking CMOS processes.

Here, we’ll illustrate the management and optimization of SoC-Power Management Integrated Circuit (PMIC) codesign considerations through the NXP i.MX 8M family of processors (Mini and Nano) and ROHM BD71847/BD71850. These solutions were selected because their combination of features, low bill of materials (BOM) cost, and compact footprint enables OEMs to quickly develop and produce smart connected devices.

Tradeoffs and Solution

Increased system-level power integration on the SoC carries several costs:

  • Decreased design flexibility
  • Sub-optimal system efficiency
  • Higher development and BOM cost
  • Longer time to market  

These tradeoffs create an opportunity for system-level innovation in building modern processors and their power subsystems.

Ways to Improve Design Flexibility

The NXP i.MX 8M/8Mini/Nano does not have integrated DC/DC converters or low-dropout regulators (LDOs). Similar SoCs also don’t integrate DC/DC converters but many use on-chip LDOs to convert an external power rail a lower voltage to the processor cores—applying Dynamic Voltage and Frequency Scaling (DVFS) to the cores. By keeping DC/DC and LDOs off chip, SoC designers fully utilized expensive 14nm silicon real estate that is optimized for digital functions such as processor cores, caches, and audio/video hardware accelerators. Unencumbered by on-chip power management requirements, they are free to formulate an (external) power architecture that facilitates rather than putting constraints on the development of the processor. The rather large number of power rails (8 bucks and 7 LDOs) required by the i.MX 8M is an indication of this freedom. At the same time, ROHM PMIC designers implemented their power circuits in ROHM’s 130nm Bipolar-CMOS-DMOS (BCD) process, which is optimized for power management functions. Each team had the freedom to use the most suitable process and IPs for the tasks at hand.

Ways to Improve System Efficiency

Implementing power circuits in 130nm BCD process allows BD71847AMWV/BD71850MWV’s (Figure 1) bucks to achieve efficiency up to 95 percent for 0.7V-3.3V output voltage. At the system level, efficiency is further improved when external DC/DC is used to directly apply DVFS to the processor core. After all, using an external DC/DC with on-chip LDO for DVFS amounts to 2-stage conversion, incurring extra loss in the 2nd stage. 

An often overlooked feature is the accuracy of output voltages (+/-1.5 percent). Along with the higher resolution in the output voltage adjustment step (10mV step), the power manager software can precisely set a power rail’s output voltage at the lowest level to minimize power consumption and yet still allows the subsystem powered by that power rail to operate at the desired frequency.

Figure 1: ROHM Semiconductor BD71850MWV PMIC integrates all power rails the i.MX 8M Nano processors and system peripherals require as well as a sequencer compatible with power modes supported by i.MX 8M Nano processors, making it possible to significantly reduce the development time, decrease size, and simplify application design. (Source: Mouser Electronics)

Ways to Lower Development and BOM Cost

With continuing market pressure to add additional features and/or to reduce product size and weight, engineers are constantly trying to find ways to integrate more functionalities into ICs and improve reliability. However, higher levels of integration can also carry higher development and die cost. Decoupling SoC development from that of power management allows each to proceed at its own optimal pace. Every step in the process—from design, verification, IC layout, to IC manufacturing—is simpler and faster and greatly improve the chance of having first-time-right silicons. The lower (total) die cost comes from implementing power functions on the cheaper (BCD) process.

Ways to Improve Time to Market

As with many technology businesses, time to market is critical. For highly complex components such as application processors, separating the developments of fundamentally incompatible technologies such as digital processing elements (CPU, hardware accelerators) and power management lower development effort and risk, which translate into faster time to market.


The considerations for designing programmable PMIC for SoC offer tradeoffs in user experience and product development. NXP’s 8M/8MM/Nano and ROHM Semiconductor’s 847/850 are highly engineered products that enable success at both ends of the product life cycle. Applications ranging from streaming media boxes and dongles to AV receivers and wireless soundbars to industrial HMI, SBC, IPC, and panel computers use these components for their robust performance. The semiconductors optimize user-critical features—performance and price—with manufacturer-friendly assets such as design flexibility and time to market. They are market-ready products that demonstrate the critical balance between the flexibility of non-integrated components and highly integrated PMIC-SoC.

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Adam KimmelAdam Kimmel has nearly 20 years as a practicing engineer, R&D manager, and engineering content writer. He creates white papers, website copy, case studies, and blog posts in vertical markets including automotive, industrial/manufacturing, technology, and electronics. Adam has degrees in chemical and mechanical engineering and is the founder and principal at ASK Consulting Solutions, LLC, an engineering and technology content writing firm.

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