STMicroelectronics SPC58 Chorus 2B Automotive Body Microcontrollers

STMicroelectronics SPC58 Chorus 2B Automotive Body Microcontrollers are part of the 32-bit General-Purpose Automotive Power Architecture® MCU portfolio. This portfolio is designed for body, networking, and convenience applications. The STMicroelectronics SPC58 Chorus 2B Line is an 80MHz single-core with up to 1Mbyte of Flash memory. It features an error-correcting code (ECC) and is pin-to-pin compatible with the SPC58 4B Line and SPC58 C Line automotive microcontrollers.

The SPC58 2B Line complies with ISO 26262 specifications and supports the ASIL-B safety standard. They are available in multiple packages ranging from a compact QFN48 up to 64- and 100-pin TQFP packages with exposed pads for high thermal efficiency.

Features

AEC-Q100 qualified
High-performance e200z2 single-core
- 32-bit Power Architecture technology CPU
- Core frequency as high as 80MHz
- Variable Length Encoding (VLE)
- Floating Point, End-to-End Error Correction
1088KB (1024KB code flash + 64KB data flash) on-chip flash memory: supports read during the program and erase operations, and multiple blocks allowing EEPROM emulation
96KB on-chip general-purpose SRAM
Multi-channel direct memory access controller (eDMA) with 16 channels
1 interrupt controller (INTC)
Comprehensive new generation ASIL-B safety concept
- ASIL-B of ISO 26262
- FCCU for collection and reaction to failure notifications
- Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
- Cyclic redundancy check (CRC) unit
- End-to-end Error Correction Code (e2eECC) logic
Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC
Junction temperature range -40°C to 150°

Body cross triggering unit (BCTU)
- Triggers ADC conversions from any eMIOS channel
- Triggers ADC conversions from up to 2 dedicated PIT_RTIs
- 1 event configuration register dedicated to each timer event allows defining the corresponding ADC channel
- Synchronization with ADC to avoid a collision
1 enhanced 12-bit SAR analog-to-digital converters
- Up to 27 channels
- Enhanced diagnosis feature
Communication interfaces
- 6 LINFlexD modules
- 4 deserial serial peripheral interface (DSPI) modules
- 7 MCAN interfaces with advanced shared memory scheme and ISO CAN FD support
Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell
Nexus Class 3 debug and trace interface
Boot assist Flash (BAF) supports factory programming using a serial bootloader through the asynchronous CAN or LIN/UART.
Enhanced modular IO subsystem (eMIOS): up to 32 timed I/O channels with a 16-bit counter resolution
Advanced and flexible supply scheme
- On-chip voltage regulator for 1.2V core logic supply.